Subversion Repositories minsoc

[/] [minsoc/] [trunk/] - Rev 58


Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 58 2011-04-28 21:50:11 GMT
  • Author: rfajardo
  • Log message:
    Standard definitions depended on implementation order. Now, this should be solved.

    minsoc_bench_defines.v: when setting reset to be positive (`define POSITIVE_RESET), NEGATIVE_RESET is undefined. This override the implementation order, so that independent of it, POSITIVE_RESET will be used.

    minsoc_defines.v: when setting GENERIC_FPGA, FPGA_TAP and FPGA_CLOCK_DIVISION are undefined. This way, even if FPGA_TAP would come prior to GENERIC_TAP on the correspondent implementation, GENERIC_TAP would still be selected.

    IMPORTANT: GENERIC_MEMORY must still be implemented first on minsoc_onchip_ram.v, because FPGA's memory is automatically selected from other definitions and cannot be undefined a priori. Since some other memory types can be selected, there is no trivial solution. However, this shouldn't be a big problem, since the beginning of this file will probably not be modified.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 58  3828d 15h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  4416d 03h root View Log RSS feed
[NODE][FOLDER] tags/ 42  3872d 23h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 58  3828d 15h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 40  3878d 21h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 58  3828d 15h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 49  3865d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 58  3828d 15h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 34  4023d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 55  3836d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 47  3866d 22h rfajardo View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2021, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.