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[/] [minsoc/] [trunk/] [backend/] - Rev 99

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Last modification

  • Rev 99 2011-09-12 09:30:45 GMT
  • Author: rfajardo
  • Log message:
    backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails.
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[FOLDER] minsoc/ 99  3180d 22h rfajardo View Log RSS feed
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[NODE][FOLDER] tags/ 42  3361d 17h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 99  3180d 22h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 99  3180d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera_3c25_board/ 99  3180d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] ml509/ 64  3312d 21h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] spartan3a_dsp_kit/ 97  3180d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] spartan3e_starter_kit/ 97  3180d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] spartan3e_starter_kit_eth/ 97  3180d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] std/ 97  3180d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 71  3305d 21h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 49  3354d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 97  3180d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 88  3186d 15h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 85  3186d 16h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 80  3204d 21h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 98  3180d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 83  3198d 22h rfajardo View Log RSS feed

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