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[/] [minsoc/] [trunk/] [bench/] - Rev 10

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  • Rev 10 2009-10-09 15:20:03 GMT
  • Author: rfajardo
  • Log message:
    Added a file containing models for each FPGA memory instances used in or1200. The file is in bench/verilog/sim_lib/fpga_memory_primitives.v.

    With it, people who change the or1200_defines.v inside of the project structure will still be able to simulate, using house-made models, not from manufacturers.

    minsoc_bench.v had to be extended by the task, init_fpga_memory, to initialize the dual or two port memories instances of or1200. This has to be done based on the type of memory used, so many different instantiations based on definitions. Somehow or1200 expects all memory values to be 0 upon start, so this is necessary.
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[NODE][NODE][FOLDER] bench/ 10  4030d 15h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 10  4030d 15h rfajardo View Log RSS feed
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[NODE][NODE][FOLDER] sim/ 10  4030d 15h rfajardo View Log RSS feed
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