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[/] [minsoc/] [trunk/] [bench/] [verilog/] - Rev 59

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Last modification

  • Rev 59 2011-04-28 21:59:30 GMT
  • Author: rfajardo
  • Log message:
    undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of minsoc_defines.v. Instead, the testbench now works with the right reset level to avoid the implementation ordering problem.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 59  4687d 05h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  5274d 17h root View Log RSS feed
[NODE][FOLDER] tags/ 42  4731d 13h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 59  4687d 05h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 40  4737d 12h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 59  4687d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 59  4687d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] sim_lib/ 27  5060d 13h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] vpi/ 4  5270d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_bench.v 59  4687d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_bench_defines.v 59  4687d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_memory_model.v 2  5274d 16h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 49  4724d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 58  4687d 06h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 34  4882d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 55  4695d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 47  4725d 13h rfajardo View Log RSS feed

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