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[/] [minsoc/] [trunk/] [bench/] [verilog/] - Rev 60

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  • Rev 60 2011-04-28 22:44:09 GMT
  • Author: rfajardo
  • Log message:
    Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation.

    minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition.
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[FOLDER] minsoc/ 60  4778d 09h rfajardo View Log RSS feed
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[NODE][FOLDER] tags/ 42  4822d 17h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 60  4778d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 40  4828d 16h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 60  4778d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 60  4778d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] sim_lib/ 27  5151d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] vpi/ 4  5361d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_bench.v 60  4778d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_bench_defines.v 60  4778d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_memory_model.v 60  4778d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 49  4815d 18h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 60  4778d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 60  4778d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 55  4786d 18h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 47  4816d 17h rfajardo View Log RSS feed

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