OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [bench/] [verilog/] [sim_lib/] - Rev 175

Rev

Changes | View Log | RSS feed

Last modification

  • Rev 27 2010-04-20 14:14:15 GMT
  • Author: rfajardo
  • Log message:
    Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, which did not output its data.

    The data was being output to doq instead of q, the declared output. doq was also not defined anywhere else.

    Icarus Verilog did not detect this, because Verilog-2001 allows internal wires to be used without being defined. To detect this errors, one can define "`default_nettype none". After doing this, Icarus Verilog detected that error and nothing else.

    doq changed to q, error corrected.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 175  3088d 01h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 153  3619d 08h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 172  3172d 01h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 175  3088d 01h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 174  3123d 04h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 162  3566d 04h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 162  3566d 04h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] sim_lib/ 27  4206d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] fpga_memory_primitives.v 27  4206d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] vpi/ 155  3586d 19h nyawn View Log RSS feed
[NODE][NODE][FOLDER] doc/ 101  3687d 12h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 158  3581d 00h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 175  3088d 01h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 166  3472d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 158  3581d 00h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 141  3625d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 170  3240d 04h ConX. View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.