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[/] [minsoc/] [trunk/] [bench/] [verilog/] [sim_lib/] - Rev 17

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Last modification

  • Rev 17 2009-11-17 14:38:49 GMT
  • Author: rfajardo
  • Log message:
    Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.

    send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)

    If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 17  3888d 11h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  3948d 16h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3948d 16h root View Log RSS feed
[NODE][FOLDER] trunk/ 17  3888d 11h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 15  3894d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 17  3888d 11h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 17  3888d 11h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] sim_lib/ 17  3888d 11h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] fpga_memory_primitives.v 17  3888d 11h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] vpi/ 4  3944d 16h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 17  3888d 11h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 17  3888d 11h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 17  3888d 11h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 11  3913d 11h rfajardo View Log RSS feed

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