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[/] [minsoc/] [trunk/] [bench/] [verilog/] [sim_lib/] - Rev 27
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Last modification
- Rev 27 2010-04-20 14:14:15 GMT
- Author: rfajardo
- Log message:
- Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, which did not output its data.
The data was being output to doq instead of q, the declared output. doq was also not defined anywhere else.
Icarus Verilog did not detect this, because Verilog-2001 allows internal wires to be used without being defined. To detect this errors, one can define "`default_nettype none". After doing this, Icarus Verilog detected that error and nothing else.
doq changed to q, error corrected.