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[/] [minsoc/] [trunk/] [prj/] - Rev 175

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  • Rev 158 2012-01-05 19:32:03 GMT
  • Author: rfajardo
  • Log message:
    Adding de2_115_board port, thanks to Richard Hasha.

    Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

    Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
    -Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

    Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

    prj/srcs extended to include jsp and interconnec_defines.v.

    spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.
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[NODE][NODE][FOLDER] bench/ 162  4425d 04h rfajardo View Log RSS feed
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[NODE][NODE][FOLDER] prj/ 158  4440d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 97  4555d 11h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] scripts/ 141  4484d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 97  4555d 11h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 158  4440d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 97  4555d 11h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 141  4484d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 175  3947d 01h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 166  4331d 10h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 158  4440d 00h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 141  4484d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 170  4099d 05h ConX. View Log RSS feed

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