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[/] [minsoc/] [trunk/] [prj/] - Rev 104

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  • Rev 104 2011-10-19 10:31:39 GMT
  • Author: rfajardo
  • Log message:
    Enabling modelsim simulation for current project definition.
    vhdl and verilog projects have to be separated:
    -prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
    -Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
    -prj/scripts/simprj.sh splitted in:
    -simvhdl.sh
    -simverilog.sh
    (they generate the input files in the right format for simulation tools)
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[NODE][NODE][FOLDER] bench/ 71  3385d 01h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 101  3251d 04h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 104  3223d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 97  3260d 02h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] scripts/ 104  3223d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 97  3260d 02h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 96  3260d 13h javieralso View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 97  3260d 02h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 104  3223d 01h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 88  3265d 18h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 104  3223d 01h rfajardo View Log RSS feed
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[NODE][NODE][FOLDER] utils/ 103  3225d 16h rfajardo View Log RSS feed

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