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[/] [minsoc/] [trunk/] [prj/] - Rev 108

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Last modification

  • Rev 108 2011-10-26 16:48:51 GMT
  • Author: rfajardo
  • Log message:
    Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

    Icarus Verilog and Altera synthesis are working as well. Job done!
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[FOLDER] minsoc/ 108  3420d 06h rfajardo View Log RSS feed
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[NODE][FOLDER] tags/ 42  3645d 09h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  3420d 06h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 105  3420d 14h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 71  3589d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 101  3455d 16h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 108  3420d 06h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 97  3464d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] scripts/ 108  3420d 06h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 97  3464d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 96  3465d 01h javieralso View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 97  3464d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 104  3427d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 88  3470d 06h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 104  3427d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 80  3488d 12h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 107  3420d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 106  3420d 12h rfajardo View Log RSS feed

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