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[/] [minsoc/] [trunk/] [prj/] - Rev 108

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Last modification

  • Rev 108 2011-10-26 16:48:51 GMT
  • Author: rfajardo
  • Log message:
    Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

    Icarus Verilog and Altera synthesis are working as well. Job done!
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[NODE][FOLDER] trunk/ 108  3175d 18h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 105  3176d 02h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 71  3345d 01h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 101  3211d 04h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 108  3175d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 97  3220d 02h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] scripts/ 108  3175d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 97  3220d 02h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 96  3220d 13h javieralso View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 97  3220d 02h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 104  3183d 01h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 88  3225d 18h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 104  3183d 01h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 80  3244d 00h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 107  3175d 21h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 106  3176d 00h rfajardo View Log RSS feed

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