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[/] [minsoc/] [trunk/] [prj/] - Rev 108

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Last modification

  • Rev 108 2011-10-26 16:48:51 GMT
  • Author: rfajardo
  • Log message:
    Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

    Icarus Verilog and Altera synthesis are working as well. Job done!
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[FOLDER] minsoc/ 108  3692d 23h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  4461d 06h root View Log RSS feed
[NODE][FOLDER] tags/ 42  3918d 01h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  3692d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 105  3693d 07h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 71  3862d 05h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 101  3728d 08h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 108  3692d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 97  3737d 07h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] scripts/ 108  3692d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 97  3737d 07h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 96  3737d 18h javieralso View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 97  3737d 07h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 104  3700d 05h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 88  3742d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 104  3700d 05h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 80  3761d 05h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 107  3693d 02h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 106  3693d 05h rfajardo View Log RSS feed

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