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[/] [minsoc/] [trunk/] [prj/] - Rev 108

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Last modification

  • Rev 108 2011-10-26 16:48:51 GMT
  • Author: rfajardo
  • Log message:
    Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

    Icarus Verilog and Altera synthesis are working as well. Job done!
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[NODE][FOLDER] trunk/ 108  4563d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 105  4563d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 71  4732d 15h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 101  4598d 18h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 108  4563d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 97  4607d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] scripts/ 108  4563d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 97  4607d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 96  4608d 04h javieralso View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 97  4607d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 104  4570d 15h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 88  4613d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 104  4570d 15h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 80  4631d 15h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 107  4563d 12h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 106  4563d 15h rfajardo View Log RSS feed

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