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[/] [minsoc/] [trunk/] [prj/] [scripts/] - Rev 108

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Last modification

  • Rev 108 2011-10-26 16:48:51 GMT
  • Author: rfajardo
  • Log message:
    Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

    Icarus Verilog and Altera synthesis are working as well. Job done!
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[FOLDER] minsoc/ 108  4625d 16h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  5393d 22h root View Log RSS feed
[NODE][FOLDER] tags/ 42  4850d 18h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  4625d 16h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 105  4625d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 71  4794d 22h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 101  4661d 01h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 108  4625d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 97  4670d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] scripts/ 108  4625d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] altprj.sh 107  4625d 19h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] simverilog.sh 108  4625d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] simvhdl.sh 108  4625d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xilinxprj.sh 108  4625d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xilinxxst.sh 108  4625d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 97  4670d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 96  4670d 10h javieralso View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 97  4670d 00h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 88  4675d 16h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 104  4632d 22h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 80  4693d 21h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 107  4625d 19h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 106  4625d 21h rfajardo View Log RSS feed

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