OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] - Rev 57

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 57 2011-04-28 21:27:09 GMT
  • Author: rfajardo
  • Log message:
    If a FPGA manufacturer is selected, the FPGA families of other manufacturers are automatically ignored.

    Some updated to comments.

    CLOCK_DIVISOR back to 5. The number does not matter much, but 1 is a bad standard number, since it should never be selected. Comment says, use NO_CLOCK_DIVISION instead.

    Changing standard FPGA back to Xilinx and Spartan3A. I'm only doing this because the synthesis examples page of wiki still assume this FPGA to be standardly selected.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 57  3143d 04h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  3730d 15h root View Log RSS feed
[NODE][FOLDER] tags/ 42  3187d 11h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 57  3143d 04h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 40  3193d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 28  3501d 10h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 49  3180d 11h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 57  3143d 04h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 57  3143d 04h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 34  3338d 10h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 55  3151d 11h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 47  3181d 10h rfajardo View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.