OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] - Rev 62

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 62 2011-04-29 10:32:37 GMT
  • Author: rfajardo
  • Log message:
    Wrapping different family modules of same manufacturer in a single module.

    minsoc_clock_manager.v: uses fpga manufacturer wrappers

    xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

    altera_pll.v: selects between different Altera FPGA families and implements the module
Path Last modification Log RSS feed
[FOLDER] minsoc/ 62  3143d 10h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  3731d 10h root View Log RSS feed
[NODE][FOLDER] tags/ 42  3188d 06h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 62  3143d 10h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 40  3194d 04h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 60  3143d 21h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 49  3181d 06h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 62  3143d 10h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 62  3143d 10h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 60  3143d 21h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 61  3143d 10h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 47  3182d 05h rfajardo View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.