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[/] [minsoc/] [trunk/] [rtl/] - Rev 62

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Last modification

  • Rev 62 2011-04-29 10:32:37 GMT
  • Author: rfajardo
  • Log message:
    Wrapping different family modules of same manufacturer in a single module.

    minsoc_clock_manager.v: uses fpga manufacturer wrappers

    xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

    altera_pll.v: selects between different Altera FPGA families and implements the module
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[NODE][NODE][FOLDER] bench/ 60  3497d 17h rfajardo View Log RSS feed
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[NODE][NODE][FOLDER] rtl/ 62  3497d 05h rfajardo View Log RSS feed
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[NODE][NODE][FOLDER] sw/ 61  3497d 06h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 47  3536d 00h rfajardo View Log RSS feed

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