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[/] [minsoc/] [trunk/] [rtl/] - Rev 70

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  • Rev 70 2011-05-10 10:06:07 GMT
  • Author: rfajardo
  • Log message:
    Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

    Removing timescale definition of minsoc_bench_defines.v files.

    Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
    -pli ../../bench/verilog/vpi/jp-io-vpi.so
    to:
    -pli ../../bench/verilog/vpi/jp-io-vpi.dll

    These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 70  3138d 17h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  3737d 17h root View Log RSS feed
[NODE][FOLDER] tags/ 42  3194d 13h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 70  3138d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 70  3138d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 69  3143d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 49  3187d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 70  3138d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 70  3138d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 70  3138d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 69  3143d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 64  3145d 16h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 64  3145d 16h rfajardo View Log RSS feed

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