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[/] [minsoc/] [trunk/] [rtl/] [verilog/] - Rev 20

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Last modification

  • Rev 20 2010-01-21 13:57:46 GMT
  • Author: rfajardo
  • Log message:
    minsoc_defines.v had a semicolon at the end of the two reset polarity definitions.

    minsoc_top had a signal array for two different signals which was for backward compatibility. The compatible debugging module is so old that there is no reason for keeping it.

    Documentation has been updated to better explain how to use the definitions files, minsoc_defines.v and or1200_defines.v. An example for Altera devices has been added too.
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[FOLDER] minsoc/ 20  4296d 14h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  4421d 18h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4421d 18h root View Log RSS feed
[NODE][FOLDER] trunk/ 20  4296d 14h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 15  4367d 10h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 17  4361d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 20  4296d 14h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 20  4296d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 20  4296d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] minsoc_startup/ 12  4379d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_clock_manager.v 2  4421d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_defines.v 20  4296d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_onchip_ram.v 7  4407d 12h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_onchip_ram_top.v 7  4407d 12h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_tc_top.v 7  4407d 12h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_top.v 20  4296d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_xilinx_internal_jtag.v 2  4421d 16h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 18  4359d 18h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 11  4386d 13h rfajardo View Log RSS feed

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