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[/] [mod_sim_exp/] [tags/] [Release_1.5/] [rtl/] [vhdl/] - Rev 95
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Last modification
- Rev 95 2013-07-16 13:25:35 GMT
- Author: JonasDC
- Log message:
- new control logic for the core, allow for greater frequencies for the multiplier.
changes:
- autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
- mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination.