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[/] [mod_sim_exp/] [tags/] [start_version/] [bench/] - Rev 2

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Last modification

  • Rev 2 2012-10-18 13:14:22 GMT
  • Author: JonasDC
  • Log message:
    First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..
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[FOLDER] mod_sim_exp/ 2  4379d 10h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 1  4381d 09h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4381d 09h root View Log RSS feed
[NODE][FOLDER] trunk/ 2  4379d 10h JonasDC View Log RSS feed

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