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[/] [mod_sim_exp/] [trunk/] - Rev 63

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Last modification

  • Rev 63 2013-02-26 14:45:30 GMT
  • Author: JonasDC
  • Log message:
    now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx
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[FOLDER] mod_sim_exp/ 63  3563d 07h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 58  3569d 00h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 49  3582d 03h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 63  3563d 07h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 46  3650d 07h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 47  3650d 07h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 63  3563d 07h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 41  3660d 09h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  3675d 01h JonasDC View Log RSS feed

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