OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 95

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 95 2013-07-16 13:25:35 GMT
  • Author: JonasDC
  • Log message:
    new control logic for the core, allow for greater frequencies for the multiplier.
    changes:
    - autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
    - mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination.
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 95  3273d 06h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 68  3405d 06h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 93  3288d 07h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 95  3273d 06h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 94  3286d 02h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 92  3288d 07h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 95  3273d 06h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 94  3286d 02h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  3524d 23h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] syn/ 94  3286d 02h JonasDC View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.