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[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 69

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Last modification

  • Rev 69 2013-03-06 15:19:04 GMT
  • Author: JonasDC
  • Log message:
    big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 69  4062d 05h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 68  4062d 08h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 49  4089d 02h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 69  4062d 05h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 46  4157d 07h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 47  4157d 07h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 69  4062d 05h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 69  4062d 05h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 65  4070d 01h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  4182d 00h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] syn/ 64  4070d 06h JonasDC View Log RSS feed

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