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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 13

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Last modification

  • Rev 13 2012-10-23 18:41:23 GMT
  • Author: JonasDC
  • Log message:
    added some descriptive comments and added check for incorrect value's of width and block_width.
    File is now according to OC design rules
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 13  4196d 21h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 1  4204d 01h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4204d 01h root View Log RSS feed
[NODE][FOLDER] trunk/ 13  4196d 21h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 3  4197d 20h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 13  4196d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 13  4196d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 13  4196d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 2  4202d 02h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 11  4196d 23h JonasDC View Log RSS feed

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