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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 6

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Last modification

  • Rev 6 2012-10-23 10:48:35 GMT
  • Author: JonasDC
  • Log message:
    Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
    added descriptive comments
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 6  4283d 01h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 1  4289d 22h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4289d 22h root View Log RSS feed
[NODE][FOLDER] trunk/ 6  4283d 01h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 3  4283d 17h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 6  4283d 01h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 6  4283d 01h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 6  4283d 01h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 2  4287d 23h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 5  4283d 01h JonasDC View Log RSS feed

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