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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 54

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Last modification

  • Rev 54 2013-02-19 21:37:39 GMT
  • Author: JonasDC
  • Log message:
    generic fifo design: correctrly inferred by xilinx and altera
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 54  4175d 02h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 1  4301d 10h root View Log RSS feed
[NODE][FOLDER] tags/ 49  4187d 05h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 54  4175d 02h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 46  4255d 10h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 47  4255d 09h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 54  4175d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 54  4175d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 54  4175d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] adder_block.vhd 12  4294d 05h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] autorun_cntrl.vhd 39  4274d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b.vhd 14  4294d 05h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_adder.vhd 9  4294d 10h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_mux.vhd 9  4294d 10h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] counter_sync.vhd 39  4274d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] d_flip_flop.vhd 4  4294d 14h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] fifo_generic.vhd 54  4175d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] fifo_primitive.vhd 3  4295d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram.vhd 3  4295d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_core.vhd 45  4255d 10h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_pkg.vhd 45  4255d 10h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_ctrl.vhd 39  4274d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_multiplier.vhd 37  4278d 05h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operands_sp.vhd 3  4295d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_dp.vhd 3  4295d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_mem.vhd 39  4274d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram.vhd 39  4274d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_1b.vhd 6  4294d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_n.vhd 15  4294d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] standard_cell_block.vhd 17  4293d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] stepping_logic.vhd 19  4292d 10h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_first_cell_logic.vhd 31  4279d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_last_cell_logic.vhd 39  4274d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_pipeline.vhd 37  4278d 05h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_stage.vhd 25  4280d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] x_shift_reg.vhd 21  4287d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 45  4255d 10h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ram/ 53  4175d 09h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 41  4265d 11h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  4280d 03h JonasDC View Log RSS feed

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