OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 67

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 67 2013-03-06 12:16:29 GMT
  • Author: JonasDC
  • Log message:
    added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 67  4127d 11h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 58  4141d 02h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 49  4154d 04h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 67  4127d 11h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 46  4222d 09h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 47  4222d 09h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 67  4127d 11h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 67  4127d 11h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 67  4127d 11h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] adder_block.vhd 12  4261d 05h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] autorun_cntrl.vhd 39  4241d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b.vhd 14  4261d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_adder.vhd 9  4261d 10h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_mux.vhd 9  4261d 10h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] counter_sync.vhd 39  4241d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] d_flip_flop.vhd 4  4261d 14h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] fifo_generic.vhd 60  4138d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] fifo_primitive.vhd 3  4262d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram.vhd 3  4262d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram_asym.vhd 67  4127d 11h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram_gen.vhd 63  4135d 09h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_core.vhd 63  4135d 09h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_pkg.vhd 65  4135d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_ctrl.vhd 39  4241d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_multiplier.vhd 37  4245d 05h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operands_sp.vhd 3  4262d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_dp.vhd 3  4262d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_mem.vhd 39  4241d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_mem_gen.vhd 63  4135d 09h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram.vhd 39  4241d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram_asym.vhd 67  4127d 11h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram_gen.vhd 63  4135d 09h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_1b.vhd 6  4261d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_n.vhd 15  4261d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] standard_cell_block.vhd 17  4260d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] std_functions.vhd 59  4138d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] stepping_logic.vhd 19  4259d 10h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_first_cell_logic.vhd 31  4246d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_last_cell_logic.vhd 39  4241d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_pipeline.vhd 37  4245d 05h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_stage.vhd 25  4247d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] x_shift_reg.vhd 21  4254d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 65  4135d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ram/ 66  4127d 11h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 65  4135d 03h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  4247d 03h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] syn/ 64  4135d 09h JonasDC View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.