OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 69

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 69 2013-03-06 15:19:04 GMT
  • Author: JonasDC
  • Log message:
    big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 69  3557d 22h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 68  3558d 00h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 49  3584d 18h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 69  3557d 22h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 46  3652d 23h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 47  3652d 23h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 69  3557d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 69  3557d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 69  3557d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] adder_block.vhd 12  3691d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] autorun_cntrl.vhd 39  3671d 16h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b.vhd 14  3691d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_adder.vhd 9  3691d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_mux.vhd 9  3691d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] counter_sync.vhd 39  3671d 16h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] d_flip_flop.vhd 4  3692d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] fifo_generic.vhd 69  3557d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] fifo_primitive.vhd 3  3692d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram.vhd 3  3692d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram_asym.vhd 67  3558d 01h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram_gen.vhd 63  3565d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_core.vhd 69  3557d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_pkg.vhd 69  3557d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_ctrl.vhd 39  3671d 16h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_multiplier.vhd 37  3675d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operands_sp.vhd 3  3692d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_dp.vhd 3  3692d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_mem.vhd 69  3557d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram.vhd 39  3671d 16h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram_asym.vhd 69  3557d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram_gen.vhd 63  3565d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_1b.vhd 6  3692d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_n.vhd 15  3691d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] standard_cell_block.vhd 17  3691d 05h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] std_functions.vhd 59  3568d 16h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] stepping_logic.vhd 19  3690d 00h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_first_cell_logic.vhd 31  3677d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_last_cell_logic.vhd 39  3671d 16h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_pipeline.vhd 37  3675d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_stage.vhd 25  3677d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] x_shift_reg.vhd 21  3685d 05h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 65  3565d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ram/ 66  3558d 01h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 65  3565d 17h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  3677d 17h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] syn/ 64  3565d 22h JonasDC View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.