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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 94

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  • Rev 94 2013-07-03 17:20:18 GMT
  • Author: JonasDC
  • Log message:
    BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
    - changed RAM and memory to support different clocks
    - new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
    - parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
    - added logic for control signals to cross from one clock domain to another
    - updated testbenches and interfaces accordingly
    - added log of synthesis of the 2 new fifo's for Xilinx
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 94  3886d 19h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 68  4005d 23h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 93  3889d 00h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 92  3889d 00h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] adder_block.vhd 12  4139d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] autorun_cntrl.vhd 39  4119d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b.vhd 14  4139d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_adder.vhd 9  4139d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_mux.vhd 9  4139d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] clk_sync.vhd 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] counter_sync.vhd 39  4119d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] d_flip_flop.vhd 4  4140d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] fifo_primitive.vhd 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram.vhd 3  4140d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram_asym.vhd 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram_gen.vhd 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_core.vhd 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_pkg.vhd 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_ctrl.vhd 39  4119d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_multiplier.vhd 37  4123d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operands_sp.vhd 3  4140d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_dp.vhd 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_mem.vhd 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram.vhd 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram_asym.vhd 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram_gen.vhd 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] pulse_cdc.vhd 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_1b.vhd 6  4140d 01h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_n.vhd 15  4139d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] standard_cell_block.vhd 17  4139d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] std_functions.vhd 59  4016d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] stepping_logic.vhd 19  4137d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_first_cell_logic.vhd 31  4125d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_last_cell_logic.vhd 39  4119d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_pipeline.vhd 37  4123d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_stage.vhd 25  4125d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] x_shift_reg.vhd 21  4133d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ram/ 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 94  3886d 19h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  4125d 16h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] syn/ 94  3886d 19h JonasDC View Log RSS feed

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