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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 95

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Last modification

  • Rev 95 2013-07-16 13:25:35 GMT
  • Author: JonasDC
  • Log message:
    new control logic for the core, allow for greater frequencies for the multiplier.
    changes:
    - autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
    - mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination.
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 95  3986d 19h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 68  4118d 19h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 93  4001d 20h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 95  3986d 19h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 92  4001d 20h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 95  3986d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 95  3986d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 95  3986d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] adder_block.vhd 12  4252d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] autorun_cntrl.vhd 95  3986d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b.vhd 14  4252d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_adder.vhd 9  4252d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_mux.vhd 9  4252d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] clk_sync.vhd 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] counter_sync.vhd 39  4232d 11h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] d_flip_flop.vhd 4  4252d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] fifo_primitive.vhd 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram.vhd 3  4253d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram_asym.vhd 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram_gen.vhd 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_core.vhd 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_pkg.vhd 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_ctrl.vhd 95  3986d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_multiplier.vhd 37  4236d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operands_sp.vhd 3  4253d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_dp.vhd 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_mem.vhd 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram.vhd 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram_asym.vhd 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram_gen.vhd 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] pulse_cdc.vhd 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_1b.vhd 6  4252d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_n.vhd 15  4252d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] standard_cell_block.vhd 17  4252d 00h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] std_functions.vhd 59  4129d 11h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] stepping_logic.vhd 19  4250d 19h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_first_cell_logic.vhd 31  4237d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_last_cell_logic.vhd 39  4232d 11h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_pipeline.vhd 37  4236d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_stage.vhd 25  4238d 12h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] x_shift_reg.vhd 21  4246d 00h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ram/ 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 94  3999d 15h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  4238d 12h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] syn/ 94  3999d 15h JonasDC View Log RSS feed

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