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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] - Rev 66

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Last modification

  • Rev 66 2013-03-06 12:05:05 GMT
  • Author: JonasDC
  • Log message:
    added asymmetric ram structures to support a more performant ramstyle.
    defined for xilinx and altera, not tested with other tools.
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 66  4054d 22h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 58  4068d 13h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 49  4081d 15h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 66  4054d 22h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 46  4149d 20h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 47  4149d 20h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 66  4054d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 66  4054d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 65  4062d 14h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 65  4062d 14h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ram/ 66  4054d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] dpramblock_asym.vhd 66  4054d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] dpram_asym.vhd 66  4054d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] dpram_generic.vhd 61  4062d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] tdpramblock_asym.vhd 66  4054d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] tdpram_asym.vhd 66  4054d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] tdpram_generic.vhd 61  4062d 22h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 65  4062d 14h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  4174d 14h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] syn/ 64  4062d 19h JonasDC View Log RSS feed

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