OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [syn/] - Rev 104

Rev

Changes | View Log | RSS feed

Last modification

  • Rev 94 2013-07-03 17:20:18 GMT
  • Author: JonasDC
  • Log message:
    BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
    - changed RAM and memory to support different clocks
    - new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
    - parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
    - added logic for control signals to cross from one clock domain to another
    - updated testbenches and interfaces accordingly
    - added log of synthesis of the 2 new fifo's for Xilinx
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 104  3324d 09h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 68  3492d 14h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 104  3324d 09h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 103  3324d 09h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 94  3373d 10h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 103  3324d 09h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 97  3359d 13h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 101  3324d 13h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 102  3324d 09h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] syn/ 94  3373d 10h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 72  3492d 11h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 94  3373d 10h JonasDC View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.