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[/] [mod_sim_exp/] [trunk/] [syn/] [xilinx/] - Rev 64

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Last modification

  • Rev 64 2013-02-26 14:49:12 GMT
  • Author: JonasDC
  • Log message:
    added synthesis reports of xilinx and altera
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 64  4098d 23h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 58  4104d 17h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 49  4117d 19h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 64  4098d 23h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 46  4186d 00h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 47  4186d 00h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 63  4098d 23h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 41  4196d 01h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  4210d 17h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] syn/ 64  4098d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 64  4098d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 64  4098d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] operands_sp.pdf 64  4098d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][DB-FILE] ver010_msec_sum.html 64  4098d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][DB-FILE] ver010_msec_syn.html 64  4098d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][DB-FILE] ver011_msec_genRAM_sum.html 64  4098d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][DB-FILE] ver011_msec_genRAM_syn.html 64  4098d 23h JonasDC View Log RSS feed

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