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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] - Rev 73

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Last modification

  • Rev 73 2021-08-27 13:24:23 GMT
  • Author: dinesha
  • Log message:
    sdram bug in FPGA mode + 8/16 bit address map fix
Path Last modification Log RSS feed
[FOLDER] sdr_ctrl/ 73  404d 01h dinesha View Log RSS feed
[NODE][FOLDER] branches/ 1  3928d 01h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3928d 01h root View Log RSS feed
[NODE][FOLDER] trunk/ 73  404d 01h dinesha View Log RSS feed
[NODE][NODE][FOLDER] doc/ 63  3886d 08h dinesha View Log RSS feed
[NODE][NODE][FOLDER] env/ 2  3924d 01h dinesha View Log RSS feed
[NODE][NODE][FOLDER] fpga/ 67  3519d 01h dinesha View Log RSS feed
[NODE][NODE][FOLDER] models/ 2  3924d 01h dinesha View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 73  404d 01h dinesha View Log RSS feed
[NODE][NODE][FOLDER] synth/ 62  3886d 09h dinesha View Log RSS feed
[NODE][NODE][FOLDER] verif/ 73  404d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][FOLDER] agents/ 2  3924d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][FOLDER] defs/ 2  3924d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][FOLDER] dump/ 10  3913d 02h dinesha View Log RSS feed
[NODE][NODE][NODE][FOLDER] lib/ 2  3924d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][FOLDER] log/ 73  404d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] core_sdr8_sim.log 65  3767d 09h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] core_sdr16_sim.log 65  3767d 09h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] core_sdr32_sim.log 65  3767d 09h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] core_SDR_8BIT_basic_test1.log 56  3887d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] core_SDR_8BIT_complie.log 73  404d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] core_SDR_16BIT_basic_test1.log 56  3887d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] core_SDR_16BIT_complie.log 73  404d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] core_SDR_32BIT_basic_test1.log 56  3887d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] core_SDR_32BIT_complie.log 73  404d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] top_sdr8_sim.log 65  3767d 09h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] top_sdr16_sim.log 65  3767d 09h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] top_sdr32_sim.log 65  3767d 09h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] top_SDR_8BIT_basic_test1.log 73  404d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] top_SDR_8BIT_complie.log 73  404d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] top_SDR_16BIT_basic_test1.log 73  404d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] top_SDR_16BIT_complie.log 73  404d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] top_SDR_32BIT_basic_test1.log 65  3767d 09h dinesha View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] top_SDR_32BIT_complie.log 73  404d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][FOLDER] model/ 32  3903d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][FOLDER] run/ 72  3397d 09h dinesha View Log RSS feed
[NODE][NODE][NODE][FOLDER] tb/ 73  404d 01h dinesha View Log RSS feed
[NODE][NODE][NODE][FOLDER] test_case/ 2  3924d 01h dinesha View Log RSS feed

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