Subversion Repositories spi_master_slave

[/] - Rev 20


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Last modification

  • Rev 20 2011-08-11 02:31:05 GMT
  • Author: jdoin
  • Log message:
    - removed folder trunk/bench.
    - added ISE13.1 complete project, with synthesis, map, place & route and timing reports. This project generates bitgen file to program a Digilent Atlys board to verify the cores in FPGA hardware, and include a simulation testbench to simulate the cores.
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