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[/] [spi_master_slave/] - Rev 5

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Last modification

  • Rev 5 2011-07-11 05:53:28 GMT
  • Author: jdoin
  • Log message:
    Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
    Added SPI line clock divider from high-speed system clock.
    Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
    Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.
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[FOLDER] spi_master_slave/ 5  3432d 14h jdoin View Log RSS feed
[NODE][FOLDER] branches/ 1  3488d 12h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3488d 12h root View Log RSS feed
[NODE][FOLDER] trunk/ 5  3432d 14h jdoin View Log RSS feed

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