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Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] - Rev 14

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Last modification

  • Rev 12 2012-02-25 10:48:40 GMT
  • Author: motilito
  • Log message:
    Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.
Path Last modification Log RSS feed
[FOLDER] uart2bus/ 14  2820d 14h motilito View Log RSS feed
[NODE][FOLDER] branches/ 1  5352d 23h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5352d 23h root View Log RSS feed
[NODE][FOLDER] trunk/ 14  2820d 14h motilito View Log RSS feed
[NODE][NODE][FOLDER] doc/ 12  4610d 08h motilito View Log RSS feed
[NODE][NODE][FOLDER] scilab/ 7  4947d 22h motilito View Log RSS feed
[NODE][NODE][FOLDER] verilog/ 12  4610d 08h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 12  4610d 08h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 12  4610d 08h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 4  5303d 22h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 2  5350d 06h motilito View Log RSS feed
[NODE][NODE][FOLDER] vhdl/ 13  3154d 04h smuller View Log RSS feed

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