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Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] - Rev 9

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Last modification

  • Rev 9 2011-11-22 10:20:52 GMT
  • Author: motilito
  • Log message:
    Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate.
Path Last modification Log RSS feed
[FOLDER] uart2bus/ 9  4539d 10h motilito View Log RSS feed
[NODE][FOLDER] branches/ 1  5187d 01h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5187d 01h root View Log RSS feed
[NODE][FOLDER] trunk/ 9  4539d 10h motilito View Log RSS feed
[NODE][NODE][FOLDER] doc/ 8  4760d 14h motilito View Log RSS feed
[NODE][NODE][FOLDER] scilab/ 7  4781d 23h motilito View Log RSS feed
[NODE][NODE][FOLDER] verilog/ 9  4539d 10h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 4  5138d 00h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 9  4539d 10h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 4  5138d 00h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 2  5184d 08h motilito View Log RSS feed
[NODE][NODE][FOLDER] vhdl/ 6  5031d 09h smuller View Log RSS feed

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