OpenCores
URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [bench/] - Rev 14

Rev

Changes | View Log | RSS feed

Last modification

  • Rev 12 2012-02-25 10:48:40 GMT
  • Author: motilito
  • Log message:
    Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.
Path Last modification Log RSS feed
[FOLDER] uart2bus/ 14  2826d 21h motilito View Log RSS feed
[NODE][FOLDER] branches/ 1  5359d 06h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5359d 06h root View Log RSS feed
[NODE][FOLDER] trunk/ 14  2826d 21h motilito View Log RSS feed
[NODE][NODE][FOLDER] doc/ 12  4616d 14h motilito View Log RSS feed
[NODE][NODE][FOLDER] scilab/ 7  4954d 04h motilito View Log RSS feed
[NODE][NODE][FOLDER] verilog/ 12  4616d 14h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 12  4616d 14h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] reg_file_model.v 2  5356d 13h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] tb_bin_uart2bus_top.v 12  4616d 14h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] tb_txt_uart2bus_top.v 12  4616d 14h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] tb_uart2bus_top.v 12  4616d 14h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] timescale.v 2  5356d 13h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart_tasks.v 12  4616d 14h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 12  4616d 14h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 4  5310d 05h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 2  5356d 13h motilito View Log RSS feed
[NODE][NODE][FOLDER] vhdl/ 13  3160d 11h smuller View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.