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URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [rtl/] - Rev 14

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Last modification

  • Rev 12 2012-02-25 10:48:40 GMT
  • Author: motilito
  • Log message:
    Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.
Path Last modification Log RSS feed
[FOLDER] uart2bus/ 14  2655d 14h motilito View Log RSS feed
[NODE][FOLDER] branches/ 1  5187d 22h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5187d 22h root View Log RSS feed
[NODE][FOLDER] trunk/ 14  2655d 14h motilito View Log RSS feed
[NODE][NODE][FOLDER] doc/ 12  4445d 07h motilito View Log RSS feed
[NODE][NODE][FOLDER] scilab/ 7  4782d 21h motilito View Log RSS feed
[NODE][NODE][FOLDER] verilog/ 12  4445d 07h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 12  4445d 07h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 12  4445d 07h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] baud_gen.v 3  5185d 04h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart2bus_top.v 12  4445d 07h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart_parser.v 12  4445d 07h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart_rx.v 9  4540d 07h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart_top.v 2  5185d 05h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart_tx.v 9  4540d 07h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 4  5138d 21h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 2  5185d 05h motilito View Log RSS feed
[NODE][NODE][FOLDER] vhdl/ 13  2989d 03h smuller View Log RSS feed

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