URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [bench/] - Rev 28

Rev 28 2010-03-09 13:12:02 GMT
Author: mikaeljf
Log message:
Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.

Path	Last modification			Log	RSS feed
versatile_mem_ctrl/	28	5185d 15h	mikaeljf	View Log	RSS feed
branches/	1	5449d 16h	root	View Log	RSS feed
tags/	1	5449d 16h	root	View Log	RSS feed
trunk/	28	5185d 15h	mikaeljf	View Log	RSS feed
backend/	8	5442d 11h	unneback	View Log	RSS feed
bench/	28	5185d 15h	mikaeljf	View Log	RSS feed
ddr/	11	5319d 07h	mikaeljf	View Log	RSS feed
fizzim.pl	9	5346d 15h	unneback	View Log	RSS feed
Makefile	18	5214d 14h	mikaeljf	View Log	RSS feed
mt48lc16m16a2.v	9	5346d 15h	unneback	View Log	RSS feed
tb.v	28	5185d 15h	mikaeljf	View Log	RSS feed
tb_defines.v	17	5217d 13h	mikaeljf	View Log	RSS feed
wb0.fzm	9	5346d 15h	unneback	View Log	RSS feed
wb0.v	9	5346d 15h	unneback	View Log	RSS feed
wb0_ddr.fzm	15	5218d 14h	mikaeljf	View Log	RSS feed
wb1.fzm	9	5346d 15h	unneback	View Log	RSS feed
wb1.v	9	5346d 15h	unneback	View Log	RSS feed
wb1_ddr.fzm	15	5218d 14h	mikaeljf	View Log	RSS feed
wb4.fzm	9	5346d 15h	unneback	View Log	RSS feed
wb4.v	9	5346d 15h	unneback	View Log	RSS feed
wb4_ddr.fzm	15	5218d 14h	mikaeljf	View Log	RSS feed
doc/	27	5189d 06h	unneback	View Log	RSS feed
rtl/	28	5185d 15h	mikaeljf	View Log	RSS feed
sim/	28	5185d 15h	mikaeljf	View Log	RSS feed
syn/	22	5201d 08h	mikaeljf	View Log	RSS feed
web_uploads/	1	5449d 16h	root	View Log	RSS feed