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[/] - Rev 118


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  • Rev 118 2016-04-02 23:29:56 GMT
  • Author: dgisselq
  • Log message:
    Fixes two bugs: 1) in the early branching code within the instruction decoder.
    This prevented the early branching from working when built with Xilinx's tools,
    while the code worked with Verilator. 2) The CPU was not working with the
    traditional cache and early branching disabled. These two bugs masked each
    other. The replacement code is simpler.
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