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[/] - Rev 15


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  • Rev 15 2015-08-12 11:44:26 GMT
  • Author: dgisselq
  • Log message:
    Updated the core CPUOPS module to make certain that the carry was properly
    set on right shifts. (Carry is then the last bit shifted out to the right,
    and has no relation to the high order bits of the word.) Also fixed a bug
    in the busdelay.v file that prevented our Quad SPI flash controller from
    working. (This bug fix has not yet been tested ...) Our test.S program, the
    closest thing we have to a regression test and found in the sw/zasm directory,
    still successfully passes in Verilator.
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