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[/] [zipcpu/] [trunk/] [rtl/] - Rev 118

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  • Rev 118 2016-04-02 23:29:56 GMT
  • Author: dgisselq
  • Log message:
    Fixes two bugs: 1) in the early branching code within the instruction decoder.
    This prevented the early branching from working when built with Xilinx's tools,
    while the code worked with Verilator. 2) The CPU was not working with the
    traditional cache and early branching disabled. These two bugs masked each
    other. The replacement code is simpler.
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[FOLDER] zipcpu/ 118  2276d 02h dgisselq View Log RSS feed
[NODE][FOLDER] branches/ 1  2527d 09h root View Log RSS feed
[NODE][FOLDER] tags/ 1  2527d 09h root View Log RSS feed
[NODE][FOLDER] trunk/ 118  2276d 02h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] bench/ 105  2300d 10h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 107  2295d 03h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 118  2276d 02h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] aux/ 69  2378d 09h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] core/ 118  2276d 02h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] peripherals/ 88  2365d 03h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] cpudefs.v 84  2367d 01h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 105  2300d 10h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] zipbones.v 105  2300d 10h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] zipsystem.v 115  2276d 09h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] sw/ 117  2276d 09h dgisselq View Log RSS feed

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