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[/] [zipcpu/] [trunk/] [rtl/] - Rev 15

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Last modification

  • Rev 15 2015-08-12 11:44:26 GMT
  • Author: dgisselq
  • Log message:
    Updated the core CPUOPS module to make certain that the carry was properly
    set on right shifts. (Carry is then the last bit shifted out to the right,
    and has no relation to the high order bits of the word.) Also fixed a bug
    in the busdelay.v file that prevented our Quad SPI flash controller from
    working. (This bug fix has not yet been tested ...) Our test.S program, the
    closest thing we have to a regression test and found in the sw/zasm directory,
    still successfully passes in Verilator.
Path Last modification Log RSS feed
[FOLDER] zipcpu/ 15  3121d 14h dgisselq View Log RSS feed
[NODE][FOLDER] branches/ 1  3138d 10h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3138d 10h root View Log RSS feed
[NODE][FOLDER] trunk/ 15  3121d 14h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] bench/ 12  3136d 06h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 10  3137d 04h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 15  3121d 14h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] aux/ 15  3121d 14h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] core/ 15  3121d 14h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] peripherals/ 9  3137d 04h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 2  3138d 05h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] zipsystem.v 11  3136d 14h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] sw/ 14  3121d 15h dgisselq View Log RSS feed

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