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[/] [zipcpu/] [trunk/] [rtl/] - Rev 65

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  • Rev 65 2015-10-22 15:59:30 GMT
  • Author: dgisselq
  • Log message:
    Lots of logic simplifications to the core, in addition to better support for
    illegal instruction detection and bus error detection. The biggest change
    had to deal with pushing the debug write interface into the ALU write
    processing path. This simplifies the logic of adjusting the PC and CC
    registers primarily, but also any writes to other registers. It also delays
    these register writes by a clock, but since the debug interface is already
    ridiculously slow I doubt that matters any.
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[FOLDER] zipcpu/ 65  3070d 19h dgisselq View Log RSS feed
[NODE][FOLDER] branches/ 1  3158d 19h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3158d 19h root View Log RSS feed
[NODE][FOLDER] trunk/ 65  3070d 19h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] bench/ 58  3070d 19h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 49  3090d 13h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 65  3070d 19h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] aux/ 61  3070d 19h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] core/ 65  3070d 19h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] peripherals/ 56  3080d 21h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] cpudefs.v 64  3070d 19h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 56  3080d 21h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] zipbones.v 56  3080d 21h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] zipsystem.v 56  3080d 21h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] sw/ 60  3070d 19h dgisselq View Log RSS feed

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