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[/] [zipcpu/] [trunk/] [rtl/] [core/] - Rev 18

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  • Rev 18 2015-08-16 00:59:04 GMT
  • Author: dgisselq
  • Log message:
    A couple of changes: Registers can now be changed via the debug interface.
    Also, in anticipation of being able to interrupt the break the processor,
    the CPU now exports an interrupt line to the external environment to tell
    when it has been halted. Thus, if it gets halted by a break instruction,
    the ZipSystem will interrupt whatever's in its environment so that the
    debugger can come and examine its state.

    Oh, and one other: because you can't examine the state of the CPU without
    halting it, I modified the debug control register to export the four
    useful flags: break-enable, interrupts enabled, and sleep (step comes for
    free in this implementation).
Path Last modification Log RSS feed
[FOLDER] zipcpu/ 18  3259d 00h dgisselq View Log RSS feed
[NODE][FOLDER] branches/ 1  3279d 09h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3279d 09h root View Log RSS feed
[NODE][FOLDER] trunk/ 18  3259d 00h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] bench/ 12  3277d 05h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 10  3278d 03h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 18  3259d 00h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] aux/ 15  3262d 13h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] core/ 18  3259d 00h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] cpuops.v 15  3262d 13h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] memops.v 3  3278d 10h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] pipefetch.v 18  3259d 00h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] prefetch.v 2  3279d 04h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] zipcpu.v 18  3259d 00h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] peripherals/ 9  3278d 03h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] sw/ 17  3259d 01h dgisselq View Log RSS feed

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