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[/] [zipcpu/] [trunk/] [rtl/] [core/] - Rev 18

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Last modification

  • Rev 18 2015-08-16 00:59:04 GMT
  • Author: dgisselq
  • Log message:
    A couple of changes: Registers can now be changed via the debug interface.
    Also, in anticipation of being able to interrupt the break the processor,
    the CPU now exports an interrupt line to the external environment to tell
    when it has been halted. Thus, if it gets halted by a break instruction,
    the ZipSystem will interrupt whatever's in its environment so that the
    debugger can come and examine its state.

    Oh, and one other: because you can't examine the state of the CPU without
    halting it, I modified the debug control register to export the four
    useful flags: break-enable, interrupts enabled, and sleep (step comes for
    free in this implementation).
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[FOLDER] zipcpu/ 18  2511d 18h dgisselq View Log RSS feed
[NODE][FOLDER] branches/ 1  2532d 03h root View Log RSS feed
[NODE][FOLDER] tags/ 1  2532d 03h root View Log RSS feed
[NODE][FOLDER] trunk/ 18  2511d 18h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] bench/ 12  2529d 23h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 10  2530d 21h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 18  2511d 18h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] aux/ 15  2515d 08h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] core/ 18  2511d 18h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] cpuops.v 15  2515d 08h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] memops.v 3  2531d 05h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] pipefetch.v 18  2511d 18h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] prefetch.v 2  2531d 22h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] zipcpu.v 18  2511d 18h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] peripherals/ 9  2530d 21h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] sw/ 17  2511d 19h dgisselq View Log RSS feed

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