URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 31

Rev	Log message	Author	Age	Path
31	fix some bugs	simont	8022d 02h	/
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	8025d 08h	/
29	fix some bugs	simont	8025d 09h	/
28	remove syn signal	simont	8025d 09h	/
27	fix some bugs	simont	8025d 09h	/
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	8025d 11h	/
25	divider and multiplier pass test	markom	8026d 06h	/
24	intensively tests all instructions	markom	8026d 11h	/
23	mul & div use 4 clocks	simont	8027d 01h	/
22	fix some bugs	simont	8027d 01h	/
21	mul bug fixed	markom	8027d 06h	/
20	multiplier and divider changed so they complete in 4 cycles	markom	8027d 09h	/
19	combinatorial loop removed	simont	8028d 01h	/
18	rst signal added	simont	8031d 07h	/
17	fix some bugs	simont	8031d 07h	/
16	inputs ram and op2 removed	simont	8031d 07h	/
15	commbinatorial loop removed	simont	8031d 07h	/
14	added signal ea_int	simont	8031d 08h	/
13	some bug fix	simont	8032d 05h	/
12	des1_r in alu port list	simont	8032d 05h	/
11	des2_r removed	simont	8032d 05h	/
10	% replaced with ^ in uart; some minor improvements	markom	8032d 11h	/
9	removed unused compare states	markom	8034d 04h	/
8	some IDS optimizations	markom	8034d 04h	/
7	immediate1 & immediate2 registers moved to oc8051_immediate_sel	markom	8034d 05h	/
6	psw combinatorial loop removed	markom	8034d 07h	/
5	more linter corrections; 2 tests still fail	markom	8034d 07h	/
4	Code repaired to satisfy the linter; testbech fails	markom	8034d 09h	/
3	This commit was manufactured by cvs2svn to create tag 'rel0'.		8050d 07h	/
2	Initial CVS import	simont	8050d 07h	/