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Rev Log message Author Age Path
46 Minor code cleanup. sybreon 6099d 03h /
45 Minor code cleanup. sybreon 6099d 03h /
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6099d 16h /
43 Added interrupt simulation.
Changed "human readable" simulation output.		 sybreon 6099d 16h /
42 Enable MSR_IE with software. sybreon 6099d 17h /
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6100d 08h /
40 Recommended to compile code with -O2/3/s sybreon 6110d 16h /
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6110d 16h /
38 Added interrupt support. sybreon 6255d 17h /
37 This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'. 6269d 02h /
36 Removed asynchronous reset signal. sybreon 6269d 02h /
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6269d 23h /
34 Corrected speed issues after rev 1.9 update. sybreon 6270d 13h /
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6285d 20h /
32 Modified compilation sequence. sybreon 6285d 20h /
31 Removed byte acrobatics. sybreon 6285d 20h /
30 Minor updates as sw/c/aeMB_testbench.c got updated. sybreon 6288d 20h /
29 Added code documentation.
Added new tests that test floating point, modulo arithmetic and multiplication/division.		 sybreon 6288d 20h /
28 Fixed simulation bug. sybreon 6288d 20h /
27 Removed some unnecessary bubble control. sybreon 6289d 07h /
26 Fixed minor synthesis bug. sybreon 6289d 07h /
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6289d 11h /
24 Made minor performance optimisations. sybreon 6289d 21h /
23 Fixed minor simulation bug. sybreon 6290d 13h /
22 Added support for 8-bit and 16-bit data types. sybreon 6290d 13h /
21 Added hierarchy block diagram. sybreon 6300d 19h /
20 Added basic documentation doc/aeMB_datasheet.pdf sybreon 6301d 09h /
19 Added initial unified memory core. sybreon 6302d 23h /
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6303d 15h /
17 Cosmetic changes sybreon 6304d 19h /

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