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Rev Log message Author Age Path
49 Actel APA ram changed. Now synchronous read is used. mohor 7903d 05h /
48 Actel APA ram supported. mohor 7903d 06h /
47 Data is latched on read. mohor 7903d 06h /
46 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7913d 04h /
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.		 mohor 7913d 04h /
44 When bit error occured while active error flag was transmitted, counter was
not incremented.		 mohor 7913d 05h /
43 Directory keeper. mohor 7913d 12h /
42 Initial version of the project. mohor 7913d 12h /
41 Incomplete sensitivity list fixed. mohor 7913d 14h /
40 Typo fixed. mohor 7913d 14h /
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7913d 14h /
38 Temporary backup version (still fully operable). mohor 7915d 04h /
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7915d 05h /
36 Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added.		 mohor 7915d 05h /
35 Several registers added. Not finished, yet. mohor 7918d 09h /
34 Errors monitoring improved. arbitration_lost improved. mohor 7920d 14h /
33 abort_tx added. mohor 7920d 14h /
32 abort_tx added. Bit destuff fixed. mohor 7920d 14h /
31 Wishbone interface added. mohor 7922d 04h /
30 CAN is working according to the specification. WB interface and more
registers (status, IRQ, ...) needs to be added.		 mohor 7922d 13h /
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7923d 10h /
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7924d 02h /
27 This file is not used. mohor 7928d 11h /
26 Backup. mohor 7928d 11h /
25 *** empty log message *** mohor 7928d 14h /
24 backup. mohor 7933d 04h /
23 Fifo corrected to be synthesizable. mohor 7946d 11h /
22 Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57).		 mohor 7947d 15h /
21 Data is stored to fifo at the end of ack stage. mohor 7948d 07h /
20 CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). mohor 7948d 08h /

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