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129 New documentation. mohor 7466d 01h /
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7468d 09h /
127 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7471d 09h /
126 run_sim.scr renamed to run_sim for VATS. mohor 7471d 09h /
125 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7473d 05h /
124 Display for VATS added. mohor 7473d 05h /
123 All flipflops are reset. mohor 7473d 06h /
122 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7476d 06h /
121 Port signals are all set to zero after reset. mohor 7476d 06h /
120 test stall_test added. mohor 7476d 09h /
119 cpu_stall_o activated as soon as bp occurs. mohor 7476d 09h /
118 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7478d 05h /
117 Define name changed. mohor 7478d 05h /
116 Data latching changed when testing WB. mohor 7478d 06h /
115 More debug data added. mohor 7478d 09h /
114 CRC generation iand verification in bench changed. mohor 7478d 11h /
113 IDCODE test improved. mohor 7478d 12h /
112 dbg_tb_defines.v not used. mohor 7479d 06h /
111 Define tap_defines.v added to test bench. mohor 7479d 06h /
110 Waiting for "ready" improved. mohor 7479d 07h /
109 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7479d 12h /
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7479d 12h /
107 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7480d 10h /
106 Sensitivity list updated. simons 7480d 10h /
105 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7481d 01h /
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7481d 01h /
103 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7481d 02h /
102 New version. mohor 7481d 02h /
101 Almost finished. mohor 7481d 03h /
100 *** empty log message *** mohor 7482d 05h /

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