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Subversion Repositories eco32

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Rev Log message Author Age Path
316 README added hellwig 3284d 08h /
315 README added hellwig 3284d 09h /
314 memory controller simulation 2 hellwig 3284d 10h /
313 memory controller simulation 1 hellwig 3284d 12h /
312 memory controller simulation 0 hellwig 3284d 13h /
311 README updated hellwig 3284d 14h /
310 verilated mc implementation with and without trace hellwig 3285d 10h /
309 multicycle simulation of ECO32, using Verilator hellwig 3286d 11h /
308 multicycle design, suitable for being verilated hellwig 3286d 15h /
307 several tests got duration.dat files hellwig 3287d 04h /
306 tool to show display output added hellwig 3287d 12h /
305 tool to show serial output added hellwig 3287d 12h /
304 Makefile updated hellwig 3289d 23h /
303 multicycle simulation control files added hellwig 3289d 23h /
302 tests updated hellwig 3290d 04h /
301 multicycle simulation source files added hellwig 3290d 12h /
300 memdelay experiment code looking better now hellwig 3290d 12h /
299 s3e-500 dac simulation corrected hellwig 3290d 13h /
298 xsa-xst-3 dac simulation corrected hellwig 3290d 13h /
297 memdelay experiment added hellwig 3290d 15h /
296 memspeed experiment added hellwig 3291d 03h /
295 tests for FPGA implementations hellwig 3291d 14h /
294 avoid ptrdiff_t warning in cpp, again hellwig 3293d 00h /
293 avoid ptrdiff_t warning in cpp hellwig 3293d 00h /
292 directory structure for FPGA implementations and simulations hellwig 3293d 05h /
291 avoid timing violations in DDR RAM circuit, new .bit files generated hellwig 3293d 06h /
290 Wishbone-compatible bus signals hellwig 3295d 06h /
289 new directory structure within fpga hellwig 3296d 03h /
288 new directory structure within fpga hellwig 3296d 03h /
287 new directory structure within fpga hellwig 3296d 03h /

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